Quarter-pel (q-pel) motion compensation (MC) is one of the features of H.264/AVC that aids in attaining a much\r\nbetter compression factor than what was possible in preceding standards. The better performance however also\r\nbrings higher requirements for computational complexity and memory access. This article describes a novel data\r\nstorage and the associated addressing scheme, together with the system architecture and FPGA implementation of\r\nH.264 q-pel MC. The proposed architecture is not only suitable for any H.264 standard block size, but also for\r\nstreams with different image sizes and frame rates. The hardware implementation of a stand alone H.264 q-pel MC\r\non FPGA has shown speeds between 95.9 fps for HD1080p frames, 229 fps for HD 720p and between 2502 and\r\n12623 fps for CIF and QCIF formats.
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